Sequential memories, such as FIFOs and LIFOs, are often used as a buffer between two circuits. These memories are referred to as a "sequential" because data is output in a predetermined sequence corresponding to the order in which it is was input. Sequential memories allow equipment operating at different input/output speeds to communicate with one another. Early sequential memories comprised shift registers which serially stored incoming data units at a desired speed and read out the stored data units at a different speed. Generally, shift register implementations of sequential memories are of limited storage and have unacceptable delay times, and therefore are unsuitable for many operations. More recently, random access memories have been developed in which pointers are used to implement the first-in, first-out or last-in, last-out I/O sequence.
While CMOS SRAM implementations are widely used, it would be desirable to increase the data rate at which a single sequential memory can operate. In CMOS SRAMs, a write to memory involves three distinct operations. First, the write bitlines are precharged to one of the voltage rails (normally V.sub.cc), after which the precharge is disabled. The two bitlines (D and D) are pulled to V.sub.cc and ground, or vice versa, depending upon the value to be written to the memory. Finally, the wordline and column select of the cell to be written to are pulsed to complete the write operation to the selected cell.
Importantly, all of the write bitlines are precharged between writing. Precharging the bitlines thus a power-consuming operation. Also, every cell which has a common wordline with the cell being written to is selected. Data stored in these cells are not overwritten, however, because the respective bitlines are not selected by the column select, and therefore, are still at the rail. Precharging the bitlines creates a high current situation due to the large number of cells that are pulsed. The operations for reading from the memory are very similar to the operations for writing to the memory, and therefore exhibit similar power losses due to the nature of the CMOS RAM cell.
To reduce the power consumption problems, a designer will normally resort to a block select architecture to reduce bitline length (which typically improves access time) and wordline length. The SRAM is thus divided into two or more separate arrays; once the first array is full, writing begins on the second array, and so on. Naturally, there is a trade-off between the number of blocks and the level of multiplexing necessary to combine the blocks together.
Nonetheless, because of the three operations needed to read to or write from a memory cell, the data rate of the sequential memory is limited. Typically, a write operation requires about ten nanoseconds to perform the write and to recover from the write (i.e., to precharge the write bitlines to one of the voltage rails to prepare for the next write). Thus, improvements to the speed of the sequential memory are more or less tied to improvements made to the speed of CMOS SRAM arrays.
Therefore, there is a need to provide a sequential memory having a high data rate using available technology.